Patent · US Active

Method of forming a field-effect transistor (FET) or other semiconductor device with front-side source and drain contacts

US10326013B2 · kind B2 · utility

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2References
9Claims
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Assignee

Inventors

Key dates

Filing dateNov 21, 2017
Grant dateJun 18, 2019
Priority date
Expiry dateNov 21, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/513

Abstract

A method is provided for forming an integrated circuit (IC) structure including trench-based semiconductor devices, e.g., trench FETs, having front-side drain contacts. The method may include forming an epitaxy region, forming a poly gate trench in the epitaxy region, forming a drain contact trench through the poly gate trench and extending below the poly gate trench, forming a poly gate in the poly gate trench, forming a front-side drain contact in the drain contact trench, and forming a source region in the epitaxy region adjacent the poly gate. The device may define a drift region from the poly gate/source intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extending into an underlying substrate or transition layer. The front-side drain contact depth may be selected to influence the device breakdown voltage. The front-side drain contacts may allow flip-chip mounting of the IC structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.