Low power flip flop circuit
US10326430B2 · kind B2 · utility
10Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Apr 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.