Implementing cascade level shifter for analog voltage
US10326450B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Jul 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuit for implementing a level shifter for translating logic signals to output voltage analog levels, and a design structure on which the subject circuit resides are provided. The circuit includes a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string is connected between an analog voltage rail and an analog ground. A plurality of level shifter cascaded inverters are connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground. An output of the level shifter is programmed by the level shifter resistor divider string connected to the cascaded inverters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.