Inventor · Rochester, MN, US

Grant P. Kesselring

37Patents
4h-index
22Co-inventors
59Inventor score

Filing activity: May 5, 2006 → Nov 4, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US8415969B1 Implementing screening for single FET compare of physically unclonable function (PUF) Electricity 18 Active
US7477075B2 CMOS output driver using floating wells to prevent leakage current Electricity 7 Expired
US9467092B1 Phased locked loop with multiple voltage controlled oscillators Electricity 7 Active
US8373486B2 Structure for a frequency adaptive level shifter circuit Electricity 4 Active
US8917126B1 Charge pump operating voltage range control using dynamic biasing Emerging Cross-Sectional Technologies 3 Active
US10361707B2 Efficient differential charge pump with sense and common mode control Electricity 3 Active
US9882552B2 Low power amplifier Electricity 3 Active
US9264052B1 Implementing dynamic phase error correction method and circuit for phase locked loop (PLL) Electricity 2 Active
US8994460B2 Implementing compact current mode logic (CML) inductor capacitor (LC) voltage controlled oscillator (VCO) for high-speed data communications Electricity 2 Active
US11146307B1 Detecting distortion in spread spectrum signals Electricity 2 Active
US8751982B2 Implementing dual speed level shifter with automatic mode control Electricity 1 Active
US9923565B2 Differential phase-frequency detector Electricity 1 Active
US9929722B1 Wire capacitor for transmitting AC signals Electricity 1 Active
US7532040B1 Programmable sensitivity frequency coincidence detection circuit and method Electricity 1 Active
US10088519B1 Electromigration monitor Electricity 1 Active
US11750180B2 High frequency AC coupled self-biased divider Electricity 0 Active
US11527953B1 Higher yielding improved matching reference circuit especially applicable for high speed mixed signal applications and phase locked loops and charge pumps Electricity 0 Active
US10969422B2 Guard ring monitor Electricity 0 Active
US10326450B2 Implementing cascade level shifter for analog voltage Electricity 0 Active
US8237510B2 Implementing phase locked loop (PLL) with enhanced locking capability with a wide range dynamic reference clock Electricity 0 Active
US11303285B1 Multi-mode design and operation for transistor mismatch immunity Electricity 0 Active
US12218120B2 Device mismatch mitigation for medium range and beyond distances Physics 0 Active
US8686782B2 Structure for a frequency adaptive level shifter circuit Electricity 0 Active
US9438209B2 Implementing clock receiver with low jitter and enhanced duty cycle Electricity 0 Active
US8513957B2 Implementing integral dynamic voltage sensing and trigger Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.