Array substrate and manufacturing method thereof
US10330997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Nov 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/40
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention provides an array substrate and a manufacturing method thereof. The array substrate includes: a backing plate, a TFT layer arranged on the backing plate, a protective layer covering the backing plate and the TFT layer, a color resist layer arranged on the protective layer, an organic planarization layer set on and covering the color resist layer and the protective layer, and a BPS light-shielding layer arranged on the organic planarization layer. The BPS light-shielding layer includes: a black matrix and a main photo spacer and a sub photo spacer arranged on the black matrix. The organic planarization layer is formed with a first recess in an area thereof that corresponds to at least a part of the black matrix and the first recess is filled up with the black matrix. By forming the first recess in the organic planarization layer and filling the first recess with the black matrix, the extent by which the black matrix projects beyond a pixel area can be reduced to prevent the black matrix from forming a barrier wall between sub-pixels that affects flowability of liquid crystal and to ensure the quality of a liquid crystal boxing process and the displaying perform…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.