Evaluating polynomials in hardware logic
US10331405B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 21, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | May 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An accurate implementation of a polynomial using floating-point or other rounded arithmetic can be generated using a plurality of hardware logic components which each implement an input polynomial such that the zeros in the input polynomial can be determined correctly. The number of different hardware logic components that are used can be reduced by analyzing the set of input polynomials and from it generating a set of polynomial components, where each polynomial in the set of input polynomials which is not also in the set of polynomial components, can be generated from a single one of the polynomial components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.