Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems
US10331447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Sep 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/451
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems is disclosed. In one aspect, a processor-based system provides a branch prediction circuit including a CRAS. Each CRAS entry within the CRAS includes an address field and a counter field. When a call instruction is encountered, a return address of the call instruction is compared to the address field of a top CRAS entry indicated by a CRAS top-of-stack (TOS) index. If the return address matches the top CRAS entry, the counter field of the top CRAS entry is incremented instead of adding a new CRAS entry for the return address. When a return instruction is subsequently encountered in the instruction stream, the counter field of the top CRAS entry is decremented if its value is greater than zero (0), or, if not, the top CRAS entry is removed from the CRAS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.