Inventor · Cary, NC, US

Anil Krishna

24Patents
6h-index
29Co-inventors
65Inventor score

Filing activity: Aug 5, 2008 → Nov 15, 2017

Most-cited inventions

PatentTitleAreaCited byStatus
US10108417B2 Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor Physics 40 Active
US8078852B2 Predictors with adaptive prediction threshold Physics 12 Active
US8103894B2 Power conservation in vertically-striped NUCA caches Emerging Cross-Sectional Technologies 9 Active
US8200905B2 Effective prefetching with multiple processors and threads Physics 8 Active
US9262170B2 Out-of-order checkpoint reclamation in a checkpoint processing and recovery core microarchitecture Physics 7 Active
US8438339B2 Cache management for a number of threads Physics 7 Active
US8364898B2 Optimizing a cache back invalidation policy Physics 5 Active
US8140825B2 Systems and methods for selectively closing pages in a memory Physics 4 Active
US8543767B2 Prefetching with multiple processors and threads via a coherency bus Physics 3 Active
US8914570B2 Selective write-once-memory encoding in a flash based disk cache memory Emerging Cross-Sectional Technologies 3 Active
US9851774B2 Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase Emerging Cross-Sectional Technologies 1 Active
US9043556B2 Optimizing a cache back invalidation policy Physics 1 Active
US8171220B2 Cache architecture with distributed state bits Emerging Cross-Sectional Technologies 1 Active
US8639886B2 Store-to-load forwarding mechanism for processor runahead mode operation Physics 1 Active
US8140767B2 Cache management through delayed writeback Physics 1 Active
US9081504B2 Write bandwidth management for flash devices Physics 1 Active
US10331447B2 Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems Physics 1 Active
US10725782B2 Providing variable interpretation of usefulness indicators for memory tables in processor-based systems Physics 0 Active
US10635446B2 Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction Emerging Cross-Sectional Technologies 0 Active
US9424159B2 Performance measurement of hardware accelerators Emerging Cross-Sectional Technologies 0 Active
US10437592B2 Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system Physics 0 Active
US9471325B2 Method and apparatus for selective renaming in a microprocessor Physics 0 Active
US8140758B2 Data reorganization in non-uniform cache access caches Physics 0 Active
US10551896B2 Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.