Bias scheme for word programming in non-volatile memory and inhibit disturb reduction
US10332599B2 · kind B2 · utility
2Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2018 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Mar 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.