LONGITUDE FLASH MEMORY SOLUTIONS LTD.
39Patents
38Active
39Granted
49Portfolio score
Filing activity: Aug 11, 2015 → Feb 13, 2023
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10593812B2 | Radical oxidation process for fabricating a nonvolatile charge trap memory device | Electricity | 6 | Active |
| US10700083B1 | Method of ONO integration into logic CMOS flow | Electricity | 5 | Active |
| US10374067B2 | Oxide-nitride-oxide stack having multiple oxynitride layers | Electricity | 3 | Active |
| US10332599B2 | Bias scheme for word programming in non-volatile memory and inhibit disturb reduction | Electricity | 2 | Active |
| US10896973B2 | Oxide-nitride-oxide stack having multiple oxynitride layers | Electricity | 1 | Active |
| US10790364B2 | SONOS stack with split nitride memory layer | Electricity | 1 | Active |
| US10706937B2 | Asymmetric pass field-effect transistor for non-volatile memory | Physics | 1 | Active |
| US11251189B2 | Gate fringing effect based channel formation for semiconductor device | Electricity | 0 | Active |
| US11361826B2 | Asymmetric pass field-effect transistor for nonvolatile memory | Physics | 0 | Active |
| US10903342B2 | Oxide-nitride-oxide stack having multiple oxynitride layers | Electricity | 0 | Active |
| US10699901B2 | SONOS ONO stack scaling | Electricity | 0 | Active |
| US10998019B2 | Low standby power with fast turn on method for non-volatile memory devices | Physics | 0 | Active |
| US11581029B2 | Low standby power with fast turn on method for non-volatile memory devices | Physics | 0 | Active |
| US10424592B2 | Method of integrating a charge-trapping gate stack into a CMOS flow | Electricity | 0 | Active |
| US11456365B2 | Memory transistor with multiple charge storing layers and a high work function gate electrode | Electricity | 0 | Active |
| US10510387B2 | Low standby power with fast turn on method for non-volatile memory devices | Physics | 0 | Active |
| US10418110B2 | Asymmetric pass field-effect transistor for nonvolatile memory | Physics | 0 | Active |
| US10784277B2 | Integration of a memory transistor into High-k, metal gate CMOS process flow | Electricity | 0 | Active |
| US10373688B2 | High voltage architecture for non-volatile memory | Electricity | 0 | Active |
| US10615289B2 | Nonvolatile charge trap memory device having a high dielectric constant blocking region | Electricity | 0 | Active |
| US11257912B2 | Sonos stack with split nitride memory layer | Electricity | 0 | Active |
| US10446656B2 | Memory transistor with multiple charge storing layers and a high work function gate electrode | Electricity | 0 | Active |
| US10418373B2 | Method of ONO stack formation | Electricity | 0 | Active |
| US10784356B2 | Embedded sonos with triple gate oxide and manufacturing method of the same | Electricity | 0 | Active |
| US12266521B2 | Oxide-nitride-oxide stack having multiple oxynitride layers | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.