Patent · US Active

3D package having edge-aligned die stack with direct inter-die wire connections

US10332899B2 · kind B2 · utility

2Cited by

2References

11Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Yi Xu · Folsom, US
Florence R. Pon · Folsom, US
Yong She · Shanghai, CN

Key dates

Filing date	Sep 29, 2017
Grant date	Jun 25, 2019
Priority date	—
Expiry date	Sep 29, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10B20/25
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.