Yong She
23Patents
3h-index
26Co-inventors
55Inventor score
Filing activity: Nov 12, 2014 → Apr 18, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9778688B2 | Flexible system-in-package solutions for wearable devices | Electricity | 5 | Active |
| US10910347B2 | Method, apparatus and system to interconnect packaged integrated circuit dies | Electricity | 5 | Active |
| US9859255B1 | Electronic device package | Electricity | 3 | Active |
| US10770434B2 | Stair-stacked dice device in a system in package, and methods of making same | Electricity | 2 | Active |
| US10332899B2 | 3D package having edge-aligned die stack with direct inter-die wire connections | Electricity | 2 | Active |
| US10396055B2 | Method, apparatus and system to interconnect packaged integrated circuit dies | Electricity | 2 | Active |
| US10727208B2 | Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same | Electricity | 1 | Active |
| US10438916B2 | Wire bond connection with intermediate contact structure | Electricity | 1 | Active |
| US11081451B2 | Die stack with reduced warpage | Electricity | 1 | Active |
| US11538746B2 | Vertical bond-wire stacked chip-scale package with application-specific integrated circuit die on stack, and methods of making same | Electricity | 0 | Active |
| US11830848B2 | Electronic device package | Electricity | 0 | Active |
| US10991679B2 | Stair-stacked dice device in a system in package, and methods of making same | Electricity | 0 | Active |
| US12046581B2 | Integrated circuit package with glass spacer | Electricity | 0 | Active |
| US11990395B2 | Joint connection of corner non-critical to function (NCTF) ball for BGA solder joint reliability (SJR) enhancement | Electricity | 0 | Active |
| US12027496B2 | Film in substrate for releasing z stack-up constraint | Electricity | 0 | Active |
| US11302671B2 | Power enhanced stacked chip scale package solution with integrated die attach film | Electricity | 0 | Active |
| US11848281B2 | Die stack with reduced warpage | Electricity | 0 | Active |
| US11742284B2 | Interconnect structure fabricated using lithographic and deposition processes | Electricity | 0 | Active |
| US11881441B2 | Stacked die semiconductor package spacer die | Electricity | 0 | Active |
| US11393788B2 | Integrated circuit package with glass spacer | Electricity | 0 | Active |
| US10930622B2 | Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same | Electricity | 0 | Active |
| US11894344B2 | Power enhanced stacked chip scale package solution with integrated die attach film | Electricity | 0 | Active |
| US10872832B2 | Pre-molded active IC of passive components to miniaturize system in package | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.