Vertical memory devices
US10332900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Nov 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A vertical memory device includes a gate structure on a peripheral circuit region of a substrate, the substrate including a cell region and the peripheral circuit region, and the gate structure including a first gate electrode, second, third, and fourth gate electrodes sequentially disposed at a plurality of levels, respectively, on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a first epitaxial layer extending through the second gate electrode on the cell region of the substrate, a channel extending through the third and fourth gate electrodes in the vertical direction on the first epitaxial layer, and a second epitaxial layer on a portion of the peripheral circuit region of the substrate adjacent the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.