Method and apparatus for performing register retiming in the presence of timing analysis exceptions
US10339238B2 · kind B2 · utility
1Cited by
48References
24Claims
0Family size
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Key dates
| Filing date | Jun 17, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Nov 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.