Benjamin Gamsa
13Patents
3h-index
5Co-inventors
45Inventor score
Filing activity: Oct 5, 2012 → Apr 11, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9529952B1 | Speculative circuit design component graphical user interface | Physics | 6 | Active |
| US8813018B1 | Method and apparatus for automatically configuring memory size | Physics | 5 | Active |
| US8929152B1 | Retiming programmable devices incorporating random access memories | Physics | 4 | Active |
| US10339244B1 | Method and apparatus for implementing user-guided speculative register retiming in a compilation flow | Physics | 3 | Active |
| US9971858B1 | Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions | Physics | 3 | Active |
| US9710591B1 | Method and apparatus for performing register retiming in the presence of timing analysis exceptions | Physics | 3 | Active |
| US9251876B1 | Retiming programmable devices incorporating random access memories | Physics | 1 | Active |
| US10586004B2 | Method and apparatus for utilizing estimations for register retiming in a design compilation flow | Physics | 1 | Active |
| US10339238B2 | Method and apparatus for performing register retiming in the presence of timing analysis exceptions | Physics | 1 | Active |
| US9489480B1 | Techniques for compiling and generating a performance analysis for an integrated circuit design | Physics | 0 | Active |
| US10157250B1 | Speculative circuit design component graphical user interface | Physics | 0 | Active |
| US10152565B2 | Methods for performing register retiming operations into synchronization regions interposed between circuits associated with different clock domains | Physics | 0 | Active |
| US10671781B2 | Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.