Method to improve transistor matching
US10339251B2 · kind B2 · utility
1Cited by
2References
11Claims
0Family size
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Key dates
| Filing date | Apr 24, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Apr 24, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.