Inventor · Frisco, TX, US

Ashesh Parikh

16Patents
4h-index
23Co-inventors
56Inventor score

Filing activity: Dec 23, 2004 → Jan 15, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US7687308B2 Method for fabricating carbon nanotube transistors on a silicon or SOI substrate Emerging Cross-Sectional Technologies 15 Active
US7772059B2 Method for fabricating graphene transistors on a silicon or SOI substrate Electricity 11 Active
US9496313B2 CMOS-based thermopile with reduced thermal conductance Electricity 4 Active
US7562333B2 Method and process for generating an optical proximity correction model based on layout density Physics 4 Active
US7985990B2 Transistor layout for manufacturing process control Electricity 3 Active
US8394681B2 Transistor layout for manufacturing process control Electricity 3 Active
US8793626B2 Computational lithography with feature upsizing Physics 1 Active
US7458058B2 Verifying a process margin of a mask pattern using intermediate stage models Electricity 1 Active
US9665675B2 Method to improve transistor matching Emerging Cross-Sectional Technologies 1 Active
US10339251B2 Method to improve transistor matching Emerging Cross-Sectional Technologies 1 Active
US8806388B2 Extraction of imaging parameters for computational lithography using a data weighting algorithm Physics 1 Active
US9853086B2 CMOS-based thermopile with reduced thermal conductance Electricity 1 Active
US7842955B2 Carbon nanotube transistors on a silicon or SOI substrate Emerging Cross-Sectional Technologies 1 Active
US8015513B2 OPC models generated from 2D high frequency test patterns Physics 0 Active
US12020124B2 Selecting optimum primary and secondary parameters to calibrate and generate an unbiased forecasting model Physics 0 Active
US11775852B2 Network optimization Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.