Memory device for controlling refreshing operation
US10339995B2 · kind B2 · utility
4Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Dec 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.