Erase-verify method for three-dimensional memories and memory system
US10340017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Nov 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.