Sense amplifier flip-flop with embedded scan logic and level shifting functionality
US10340900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2016 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Dec 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.