Michael A. Dreesen
16Patents
4h-index
17Co-inventors
53Inventor score
Filing activity: Dec 15, 2006 → Sep 22, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9411391B2 | Multistage low leakage address decoder using multiple power modes | Physics | 15 | Active |
| US9189052B2 | Voltage regulation for data retention in a volatile memory | Physics | 13 | Active |
| US9411392B2 | Global write driver for memory array structure | Physics | 11 | Active |
| US9529533B1 | Power grid segmentation for memory arrays | Emerging Cross-Sectional Technologies | 5 | Active |
| US8832508B2 | Apparatus and methods for testing writability and readability of memory cell arrays | Physics | 3 | Active |
| US9792979B1 | Process, voltage, and temperature tracking SRAM retention voltage regulator | Physics | 3 | Active |
| US8947967B2 | Shared integrated sleep mode regulator for SRAM memory | Physics | 2 | Active |
| US10340900B2 | Sense amplifier flip-flop with embedded scan logic and level shifting functionality | Physics | 2 | Active |
| US9412469B1 | Weak bit detection using on-die voltage modulation | Physics | 1 | Active |
| US8385140B2 | Memory elements having shared selection signals | Physics | 1 | Active |
| US8509017B2 | Memory device and related operating methods | Physics | 0 | Active |
| US11755050B2 | Adaptive current mirror circuit for current shaping with temperature | Physics | 0 | Active |
| US7724578B2 | Sensing device for floating body cell memory and method thereof | Physics | 0 | Active |
| US10812081B1 | Output signal control during retention mode operation | Electricity | 0 | Active |
| US12333357B2 | Memory bit cell for in-memory computation | Electricity | 0 | Active |
| US11688437B2 | Amplifier offset cancelation | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.