Combined analog architecture and functionality in a mixed-signal array
US10345377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Apr 3, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.