Bert Sullam
46Patents
13h-index
32Co-inventors
81Inventor score
Filing activity: Nov 28, 1994 → Dec 16, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7076420B1 | Emulator chip/board architecture and interface | Physics | 122 | Expired |
| US6614320B1 | System and method of providing a programmable clock architecture for an advanced microcontroller | Physics | 110 | Expired |
| US5697789A | Method and system for aiding foreign language instruction | Physics | 74 | Expired |
| US7308608B1 | Reconfigurable testing system and method | Physics | 74 | Expired |
| US6859884B1 | Method and circuit for allowing a microprocessor to change its operating frequency on-the-fly | Emerging Cross-Sectional Technologies | 64 | Expired |
| US6967511B1 | Method for synchronizing and resetting clock signals supplied to multiple programmable analog blocks | Electricity | 62 | Expired |
| US6950954B1 | Method and circuit for synchronizing a write operation between an on-chip microprocessor and an on-chip programmable analog device operating at different frequencies | Physics | 61 | Expired |
| US7023257B1 | Architecture for synchronizing and resetting clock signals supplied to multiple programmable analog blocks | Electricity | 61 | Expired |
| US8026739B2 | System level interconnect with programmable switching | Electricity | 55 | Active |
| US8487655B1 | Combined analog architecture and functionality in a mixed-signal array | Emerging Cross-Sectional Technologies | 52 | Active |
| US5882202A | Method and system for aiding foreign language instruction | Physics | 44 | Expired |
| US7737724B2 | Universal digital block interconnection and channel routing | Electricity | 26 | Active |
| US8135884B1 | Programmable interrupt routing system | Physics | 18 | Active |
| US9143134B1 | Combined analog architecture and functionality in a mixed-signal array | Emerging Cross-Sectional Technologies | 13 | Active |
| US8601254B1 | Configurable reset pin for input/output port | Electricity | 9 | Active |
| US8516025B2 | Clock driven dynamic datapath chaining | Electricity | 9 | Active |
| US8402313B1 | Reconfigurable testing system and method | Physics | 9 | Active |
| US7479913B1 | Configurable analog to digital converter | Electricity | 9 | Active |
| US8112551B2 | Addressing scheme to allow flexible mapping of functions in a programmable logic array | Physics | 9 | Active |
| US8476928B1 | System level interconnect with programmable switching | Electricity | 8 | Active |
| US8482313B2 | Universal digital block interconnection and channel routing | Electricity | 7 | Active |
| US8125360B1 | On-chip calibration method | Electricity | 6 | Active |
| US7555664B2 | Independent control of core system blocks for power optimization | Physics | 4 | Active |
| US8598908B1 | Built in system bus interface for random access to programmable logic registers | Physics | 4 | Active |
| US8838852B1 | Programmable interrupt routing system | Physics | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.