Memory arrangement for tensor data
US10346093B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Mar 16, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed circuitry includes RAM circuits, a memory controller, and an array of processing circuits. Each RAM circuit includes a read port and a write port. The memory controller accesses tensor data arranged in banks of tensor buffers in the RAM circuits. The memory controller is coupled to each read port by shared read control signal lines and to each write port by shared write control signal lines. The memory controller generates read control and write control signals for accessing different ones of the tensor buffers at different times. The array of processing circuits is coupled to one of the RAM circuits. The array includes multiple rows and multiple of columns of processing circuits for performing tensor operations on the tensor data. The processing circuits in each row in each array of processing circuits are coupled to input the same tensor data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.