Hardware accelerator for platform firmware integrity check
US10346343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2016 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Mar 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Encryption of a BIOS using a programmable logic device (PLD) is described. A PLD may include a static random-access memory area including programmable logic in a Lookup Table to receive a request to authenticate a basic input/output system (BIOS) executing on a processor coupled to the PLD. The PLD may calculate a hash value of a message associated with the BIOS using a Secure Hash Algorithm (SHA). The PLD may also include a random-access memory area including a first embedded random access memory block (EBR) to store a first portion of a 256-bit message digest associated with the message, a fifth portion of the 256-bit message digest, and second, third, fourth, sixth, seventh, and eighth EBRs to store second, third, fourth, sixth, seventh, and eighth portions of the 256-bit message digest, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.