Inclusion and configuration of a transaction converter circuit block within an integrated circuit
US10346572B1 · kind B1 · utility
3Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Sep 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of circuit design can include detecting, using a processor, a transactional inefficiency within trace data including transactions involving a first circuit block of a circuit design and, in response to the detecting, generating a modified version of the circuit design by including a transaction converter circuit block within the circuit design. The transaction converter circuit block can be coupled to the first circuit block and can be adapted to correct the transactional inefficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.