Method and system for performing incremental post layout simulation with layout edits
US10346573B1 · kind B1 · utility
2Cited by
93References
20Claims
0Family size
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Key dates
| Filing date | Sep 30, 2015 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Nov 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved method, system, and computer program product to perform post-layout simulation of an electronic design is provided. According to one approach, a circuit design is divided into multiple partitions for simulation. Simulation is then performed using the established partitions and results are obtained for the different partitions. When any layout editing occurs, identification can be made of any partitions that have been affected by the editing. The affected partitions are re-processed for simulation. The unaffected partitions do not necessarily need to be reprocessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.