Inventor · Antibes, FR

Arnold Ginetti

86Patents
23h-index
83Co-inventors
91Inventor score

Filing activity: Feb 10, 1993 → Jun 30, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US5841663A Apparatus and method for synthesizing integrated circuits using parameterized HDL modules Physics 333 Expired
US5426591A Apparatus and method for improving the timing performance of a circuit Physics 93 Expired
US5396435A Automated circuit design system and method for reducing critical path delay times Physics 86 Expired
US6622291B1 Method and apparatus for physical budgeting during RTL floorplanning Physics 76 Expired
US5764525A Method for improving the operation of a circuit through iterative substitutions and performance analyses of datapath cells Physics 72 Expired
US5726902A Method and apparatus for characterizing timing behavior of datapaths for integrated circuit design and fabrication Physics 70 Expired
US5956257A Automated optimization of hierarchical netlists Physics 53 Expired
US8046730B1 Systems and methods of editing cells of an electronic circuit design Physics 46 Active
US5896299A Method and a system for fixing hold time violations in hierarchical designs Physics 42 Expired
US6170080A Method and system for floorplanning a circuit design at a high level of abstraction Physics 42 Expired
US5825658A Method and a system for specifying and automatically analyzing multiple clock timing constraints in a VLSI circuit Physics 38 Expired
US7555739B1 Method and apparatus for maintaining synchronization between layout clones Physics 35 Active
US5751596A Automated system and method for identifying critical timing paths in integrated circuit layouts for use with automated circuit layout system Physics 33 Expired
US6622290B1 Timing verification method employing dynamic abstraction in core/shell partitioning Physics 31 Expired
US8719754B1 System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters Physics 30 Active
US9779193B1 Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations Physics 30 Active
US9223915B1 Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabrics Physics 28 Active
US6113647A Computer aided design system and method using hierarchical and flat netlist circuit representations Physics 27 Expired
US8281272B1 System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters Physics 25 Active
US6405345B1 Updating placement during technology mapping Physics 25 Expired
US5638290A Method for eliminating a false critical path in a logic circuit Emerging Cross-Sectional Technologies 24 Expired
US8255845B2 System and method for generating flat layout Physics 23 Active
US7949987B1 Method and system for implementing abstract layout structures with parameterized cells Physics 23 Active
US7634743B1 Method for updating a placed and routed netlist Physics 22 Active
US8806405B2 Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design Physics 22 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.