Self-optimized power management for DDR-compatible memory systems
US10347306B2 · kind B2 · utility
6Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2016 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Feb 8, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes a plurality of memory components, an in-memory power manager, and an interface to a host computer over a memory bus. The in-memory power manager is configured to control a transition of a power state of the memory module. The transition of the power state of the memory module includes a direct transition from a low power down state to a maximum power down state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.