Method and apparatus for bipolar memory write-verify
US10347314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Aug 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.