Semiconductor memory device and operating method thereof
US10347339B2 · kind B2 · utility
2Cited by
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14Claims
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Key dates
| Filing date | Jun 15, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Jun 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage, to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.