Package substrate and semiconductor package including the same
US10347576B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Sep 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a package substrate, the package substrate including a conductive plate, an insulating plate on the conductive plate, the insulating plate including a mounting region and a peripheral region surrounding the mounting region, and at least one capillary channel in the peripheral region, a semiconductor chip on the mounting region of the insulating plate, and a molding member on the insulating plate to cover the semiconductor chip, a portion of the molding member being in the at least one capillary channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.