Integrated circuit (IC) devices with varying diameter via layer
US10347592B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Nov 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) device includes a device layer and a passivation layer, where the passivation layer has vias formed in an interior region of the passivation layer that are larger than vias formed in a perimeter region of the passivation layer. As such, a varying diameter via layer is provided. The interior region vias may be configured to reduce a risk of damage to the IC device due to tensile stress, with sizes or shapes selected based on the amount of tensile stress expected to occur during subsequent use of the IC device. The perimeter region vias may be configured to reduce a risk of damage to the IC device due to sheer stress, with sizes or shapes selected based on the amount of sheer stress expected to occur during subsequent assembly or use of the IC device. Method and apparatus examples are described for use with flip-chip dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.