Method for fabricating static random access memory having insulating layer with different thicknesses
US10347645B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Dec 2, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Dec 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate comprises a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.