Patent · US Active

Skew control

US10348279B2 · kind B2 · utility

2Cited by
14References
3Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 11, 2017
Grant dateJul 9, 2019
Priority date
Expiry dateMay 11, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L7/00
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device comprises multiple sub-circuits belonging to different clock domains. The clock distribution network comprises a clock source operable for providing a global clock signal, at least one programmable delay line associated with a certain sub-circuit operable for generating a local clock signal for said sub-circuit by delaying the global clock signal or a signal derived therefrom and a global skew control circuit for managing clock skew between the local clock signals. The global skew control circuit is operable for managing clock skew between at least some local clock signals by regularly adjusting the delay caused by at least one programmable delay line when in a deskewing operating mode, and disabling adjusting the delays of the programmable delay lines when in a locked operating mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.