Memory decision feedback equalizer bias level generation
US10348534B1 · kind B1 · utility
6Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Jan 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.