Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures
US10348537B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | May 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4917
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel. The example method may further include, based on the comparison, applying an offset delay to a control signal configured to control transition of a signal line of the channel from a value associated with the current channel state to a value associated with the next channel state. The example method may further include after application of the offset delay, driving the signal line to the value associated with the next channel state responsive to the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.