Fused shader programs
US10353591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Mar 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improvements in compute shader programs executed on parallel processing hardware are disclosed. An application or other entity defines a sequence of shader programs to execute. Each shader program defines inputs and outputs which would, if unmodified, execute as loads and stores to a general purpose memory, incurring high latency. A compiler combines the shader programs into groups that can operate in a lower-latency, but lower-capacity local data store memory. The boundaries of these combined shader programs are defined by several aspects including where memory barrier operations are to execute, whether combinations of shader programs can execute using only the local data store and not the global memory (except for initial reads and writes) and other aspects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.