Apparatuses and methods for single level cell caching
US10353615B2 · kind B2 · utility
1Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2018 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.