Memory system and error correcting method of the same
US10353770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Nov 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs; re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and re-determining whether a miscorrection occurs in the re-correcting of the error of the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.