Memory cell having multi-level word line
US10354952B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Oct 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell comprises a first word line in a first layer on a first level. The memory cell also comprises a second word line having a first portion in the first layer and a second portion in a second layer. The second layer is on a second level different from the first level. The memory cell further comprises a first via layer coupling the first portion of the second word line with the second portion of the second word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.