Barrier layer for interconnects in 3D integrated device
US10354975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2016 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Sep 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on. A high-temperature treatment and functional testing of the vertically integrated electronic device may be conducted after each stack sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.