Anti-resonance structure for dampening die package resonance
US10355661B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2018 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Aug 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L25/0657
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power delivery network, circuit, and method reduce die package resonance of an integrated circuit (IC) die. Decoupling capacitors interact with equivalent series inductances (ESLs) of power conductors within a package carrier substrate create the die package resonance characteristic. In one form, an anti-resonance tuning circuit has a first node conductively coupled to one of the IC die's positive or negative power supply conductors, and a second node conductively coupled directly to a selected conductive structure on the carrier substrate. The anti-resonance tuning circuit includes a tuning capacitor, a tuning inductor, and optionally a dampening resistor coupled in series and having values sufficient to mitigate the die package resonance. In another form, impedance adjustment techniques are provided to connect and tune the anti-resonance tuning circuit to lower an impedance peak.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.