Level shifting circuit with conditional body biasing of transistors
US10355694B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2018 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Apr 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifting circuit receives a first input signal and complement of the first input signal as inputs and generates a level shifted first output signal and complement of the first output signal as outputs. The level shifting circuit includes a number of transistors that support body biasing. One set of body bias signals applied to certain ones of those transistors is generated as a function of the logical combination of the first input signal and the first output signal. Another set of body bias signals applied to certain other ones of those transistors is generated as a function of the logical combination of the complement of the first input signal and the complement of the first output signal. The conditional body bias applied to the transistors of the level shifting circuit makes the circuit operational for level shift at very low supply voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.