Inventor · Rohtak, IN

Ravinder Kumar

43Patents
7h-index
64Co-inventors
68Inventor score

Filing activity: Sep 30, 2008 → Jun 11, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US7808929B2 Efficient ACL lookup algorithms Electricity 129 Active
US11237880B1 Dataflow all-reduce for reconfigurable processor systems Physics 20 Active
US11182221B1 Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS) Physics 16 Active
US11200096B1 Resource allocation for reconfigurable processors Electricity 13 Active
US11392740B2 Dataflow function offload to reconfigurable processors Physics 12 Active
US11182264B1 Intra-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS) Physics 11 Active
US9473135B2 Driver circuit including driver transistors with controlled body biasing Electricity 7 Active
US9306550B2 Schmitt trigger in FDSOI technology Electricity 6 Active
US11625284B2 Inter-node execution of configuration files on reconfigurable processors using smart network interface controller (smartnic) buffers Physics 5 Active
US10355694B1 Level shifting circuit with conditional body biasing of transistors Electricity 5 Active
US11609798B2 Runtime execution of configuration files on reconfigurable processors with varying configuration granularity Physics 4 Active
US11847395B2 Executing a neural network graph using a non-homogenous set of reconfigurable processors Physics 4 Active
US10135749B2 Mainframe migration tools Electricity 4 Active
US11886930B2 Runtime execution of functions across reconfigurable processor Physics 4 Active
US11625283B2 Inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers Physics 4 Active
US11893424B2 Training a neural network using a non-homogenous set of reconfigurable processors Physics 3 Active
US11886931B2 Inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers Physics 3 Active
US11782729B2 Runtime patching of configuration files Physics 2 Active
US11809908B2 Runtime virtualization of reconfigurable data flow resources Physics 1 Active
US12210468B2 Data transfer between accessible memories of multiple processors incorporated in coarse-grained reconfigurable (CGR) architecture within heterogeneous processing system using one memory to memory transfer operation Physics 1 Active
US12181971B1 Symbol rotation of cache line codewords for increased reliability with metadata Physics 1 Active
US12261623B2 Decoding metadata encoded in error correction codes Electricity 0 Active
US12340195B2 Handling interrupts from a virtual function in a system with a reconfigurable processor Physics 0 Active
US12413530B2 Data processing system with link-based resource allocation for reconfigurable processors Electricity 0 Active
US12008417B2 Interconnect-based resource allocation for reconfigurable processors Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.