Non-intrusive on-chip analog test/trim/calibrate subsystem
US10359469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Dec 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3177
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An on-chip built-in self-test (BIST) circuit (10) uses a controller (16), analog-to-digital converter (ADC) (15), and digital-to-analog converter (DAC) (12) to sense voltage and/or temperature measures at predetermined circuit locations (19), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus (13) to the analog block, and to process analog test signals received over a second bus (14) from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.