High performance interconnect link layer
US10360098B2 · kind B2 · utility
3Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2016 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Sep 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.