Robert G. Blankenship
121Patents
12h-index
126Co-inventors
89Inventor score
Filing activity: Aug 27, 2001 → Jan 22, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6681292B2 | Distributed read and write caching implementation for optimized input/output applications | Physics | 179 | Expired |
| US7210000B2 | Transmitting peer-to-peer transactions through a coherent interface | Physics | 39 | Expired |
| US7949794B2 | PCI express enhancements and extensions | Emerging Cross-Sectional Technologies | 37 | Active |
| US8230120B2 | PCI express enhancements and extensions | Emerging Cross-Sectional Technologies | 17 | Active |
| US7899943B2 | PCI express enhancements and extensions | Emerging Cross-Sectional Technologies | 15 | Active |
| US8099523B2 | PCI express enhancements and extensions including transactions having prefetch parameters | Emerging Cross-Sectional Technologies | 15 | Active |
| US7165131B2 | Separating transactions into different virtual channels | Physics | 14 | Expired |
| US9639490B2 | Ring protocol for low latency interconnect switch | Physics | 13 | Active |
| US8230119B2 | PCI express enhancements and extensions | Emerging Cross-Sectional Technologies | 13 | Active |
| US7930566B2 | PCI express enhancements and extensions | Emerging Cross-Sectional Technologies | 12 | Active |
| US10552253B2 | Multichip package link error detection | Emerging Cross-Sectional Technologies | 12 | Active |
| US10552357B2 | Multichip package link | Emerging Cross-Sectional Technologies | 12 | Active |
| US9626321B2 | High performance interconnect | Emerging Cross-Sectional Technologies | 12 | Active |
| US7360027B2 | Method and apparatus for initiating CPU data prefetches by an external agent | Physics | 12 | Expired |
| US8073981B2 | PCI express enhancements and extensions | Emerging Cross-Sectional Technologies | 12 | Active |
| US7996572B2 | Multi-node chipset lock flow with peer-to-peer non-posted I/O requests | Physics | 11 | Active |
| US9355058B2 | High performance interconnect physical layer | Physics | 11 | Active |
| US7546422B2 | Method and apparatus for the synchronization of distributed caches | Physics | 10 | Expired |
| US9229897B2 | Embedded control channel for high speed serial interconnect | Physics | 9 | Active |
| US11816036B2 | Method and system for performing data movement operations with read snapshot and in place write update | Physics | 9 | Active |
| US8447888B2 | PCI express enhancements and extensions | Emerging Cross-Sectional Technologies | 9 | Active |
| US8549183B2 | PCI express enhancements and extensions | Emerging Cross-Sectional Technologies | 9 | Active |
| US9183171B2 | Fast deskew when exiting low-power partial-width high speed link state | Emerging Cross-Sectional Technologies | 9 | Active |
| US7089362B2 | Cache memory eviction policy for combining write transactions | Physics | 9 | Expired |
| US8046539B2 | Method and apparatus for the synchronization of distributed caches | Physics | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.