Metal interconnect processing for an integrated circuit metal stack
US10361095B2 · kind B2 · utility
0Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2018 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | May 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.