High-K metal gate and method for fabricating the same
US10361133B2 · kind B2 · utility
3Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Sep 18, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Oct 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.